cpldfit: version M.70d Xilinx Inc. Fitter Report Design Name: main Date: 7-11-2014, 1:47AM Device Used: XC9572XL-5-PC44 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 27 /72 ( 37%) 52 /360 ( 14%) 30 /216 ( 14%) 26 /72 ( 36%) 34 /34 (100%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 8/18 9/54 16/90 9/ 9* FB2 6/18 6/54 10/90 9/ 9* FB3 8/18 8/54 16/90 9/ 9* FB4 5/18 7/54 10/90 7/ 7* ----- ----- ----- ----- 27/72 30/216 52/360 34/34 * - Resource is exhausted ** Global Control Resources ** Signal 'CLOCK' mapped onto global clock net GCK2. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 8 8 | I/O : 28 28 Output : 25 25 | GCK/IO : 3 3 Bidirectional : 0 0 | GTS/IO : 2 2 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 34 34 ** Power Data ** There are 27 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'main.ise'. INFO:Cpld - Inferring BUFG constraint for signal 'CLOCK' based upon the LOC constraint 'P6'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. ************************* Summary of Mapped Logic ************************ ** 25 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State B_OUT<3> 2 3 FB1_2 1 I/O O STD FAST RESET B_OUT<4> 2 3 FB1_5 2 I/O O STD FAST RESET B_OUT<5> 2 3 FB1_6 3 I/O O STD FAST RESET B_OUT<6> 2 3 FB1_8 4 I/O O STD FAST RESET HSYNC 2 3 FB1_9 5 GCK/I/O O STD FAST RESET G_OUT<0> 2 3 FB1_14 7 GCK/I/O O STD FAST RESET G_OUT<1> 2 3 FB1_15 8 I/O O STD FAST RESET G_OUT<2> 2 3 FB1_17 9 I/O O STD FAST RESET PCLOCK 1 1 FB2_11 40 GTS/I/O O STD FAST B_OUT<0> 2 3 FB2_14 42 GTS/I/O O STD FAST RESET B_OUT<1> 2 3 FB2_15 43 I/O O STD FAST RESET B_OUT<2> 2 3 FB2_17 44 I/O O STD FAST RESET G_OUT<3> 2 3 FB3_2 11 I/O O STD FAST RESET G_OUT<4> 2 3 FB3_5 12 I/O O STD FAST RESET G_OUT<5> 2 3 FB3_8 13 I/O O STD FAST RESET G_OUT<6> 2 3 FB3_9 14 I/O O STD FAST RESET VSYNC 2 3 FB3_11 18 I/O O STD FAST RESET CSYNC 2 3 FB3_15 20 I/O O STD FAST RESET R_OUT<1> 2 3 FB3_16 24 I/O O STD FAST RESET R_OUT<0> 2 3 FB3_17 22 I/O O STD FAST RESET R_OUT<2> 2 3 FB4_2 25 I/O O STD FAST RESET R_OUT<3> 2 3 FB4_5 26 I/O O STD FAST RESET R_OUT<4> 2 3 FB4_8 27 I/O O STD FAST RESET R_OUT<5> 2 3 FB4_11 28 I/O O STD FAST RESET R_OUT<6> 2 3 FB4_14 29 I/O O STD FAST RESET ** 2 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State count_int<0> 1 2 FB2_16 STD RESET count_int<1> 2 3 FB2_18 STD RESET ** 9 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use CLOCK FB1_11 6 GCK/I/O GCK N64_DATA<2> FB2_2 35 I/O I N64_DATA<3> FB2_5 36 I/O I N64_DATA<4> FB2_6 37 I/O I N64_DATA<5> FB2_8 38 I/O I N64_DATA<6> FB2_9 39 GSR/I/O I DSYNC FB3_14 19 I/O I N64_DATA<0> FB4_15 33 I/O I N64_DATA<1> FB4_17 34 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 9/45 Number of signals used by logic mapping into function block: 9 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 (b) B_OUT<3> 2 0 0 3 FB1_2 1 I/O O (unused) 0 0 0 5 FB1_3 (b) (unused) 0 0 0 5 FB1_4 (b) B_OUT<4> 2 0 0 3 FB1_5 2 I/O O B_OUT<5> 2 0 0 3 FB1_6 3 I/O O (unused) 0 0 0 5 FB1_7 (b) B_OUT<6> 2 0 0 3 FB1_8 4 I/O O HSYNC 2 0 0 3 FB1_9 5 GCK/I/O O (unused) 0 0 0 5 FB1_10 (b) (unused) 0 0 0 5 FB1_11 6 GCK/I/O GCK (unused) 0 0 0 5 FB1_12 (b) (unused) 0 0 0 5 FB1_13 (b) G_OUT<0> 2 0 0 3 FB1_14 7 GCK/I/O O G_OUT<1> 2 0 0 3 FB1_15 8 I/O O (unused) 0 0 0 5 FB1_16 (b) G_OUT<2> 2 0 0 3 FB1_17 9 I/O O (unused) 0 0 0 5 FB1_18 (b) Signals Used by Logic in Function Block 1: N64_DATA<0> 4: N64_DATA<3> 7: N64_DATA<6> 2: N64_DATA<1> 5: N64_DATA<4> 8: count_int<0> 3: N64_DATA<2> 6: N64_DATA<5> 9: count_int<1> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs B_OUT<3> ...X...XX............................... 3 B_OUT<4> ....X..XX............................... 3 B_OUT<5> .....X.XX............................... 3 B_OUT<6> ......XXX............................... 3 HSYNC .X.....XX............................... 3 G_OUT<0> X......XX............................... 3 G_OUT<1> .X.....XX............................... 3 G_OUT<2> ..X....XX............................... 3 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 6/48 Number of signals used by logic mapping into function block: 6 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 (b) (unused) 0 0 0 5 FB2_2 35 I/O I (unused) 0 0 0 5 FB2_3 (b) (unused) 0 0 0 5 FB2_4 (b) (unused) 0 0 0 5 FB2_5 36 I/O I (unused) 0 0 0 5 FB2_6 37 I/O I (unused) 0 0 0 5 FB2_7 (b) (unused) 0 0 0 5 FB2_8 38 I/O I (unused) 0 0 0 5 FB2_9 39 GSR/I/O I (unused) 0 0 0 5 FB2_10 (b) PCLOCK 1 0 0 4 FB2_11 40 GTS/I/O O (unused) 0 0 0 5 FB2_12 (b) (unused) 0 0 0 5 FB2_13 (b) B_OUT<0> 2 0 0 3 FB2_14 42 GTS/I/O O B_OUT<1> 2 0 0 3 FB2_15 43 I/O O count_int<0> 1 0 0 4 FB2_16 (b) (b) B_OUT<2> 2 0 0 3 FB2_17 44 I/O O count_int<1> 2 0 0 3 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: DSYNC 3: N64_DATA<1> 5: count_int<0> 2: N64_DATA<0> 4: N64_DATA<2> 6: count_int<1> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs PCLOCK X....................................... 1 B_OUT<0> .X..XX.................................. 3 B_OUT<1> ..X.XX.................................. 3 count_int<0> X...X................................... 2 B_OUT<2> ...XXX.................................. 3 count_int<1> X...XX.................................. 3 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 8/46 Number of signals used by logic mapping into function block: 8 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) G_OUT<3> 2 0 0 3 FB3_2 11 I/O O (unused) 0 0 0 5 FB3_3 (b) (unused) 0 0 0 5 FB3_4 (b) G_OUT<4> 2 0 0 3 FB3_5 12 I/O O (unused) 0 0 0 5 FB3_6 (b) (unused) 0 0 0 5 FB3_7 (b) G_OUT<5> 2 0 0 3 FB3_8 13 I/O O G_OUT<6> 2 0 0 3 FB3_9 14 I/O O (unused) 0 0 0 5 FB3_10 (b) VSYNC 2 0 0 3 FB3_11 18 I/O O (unused) 0 0 0 5 FB3_12 (b) (unused) 0 0 0 5 FB3_13 (b) (unused) 0 0 0 5 FB3_14 19 I/O I CSYNC 2 0 0 3 FB3_15 20 I/O O R_OUT<1> 2 0 0 3 FB3_16 24 I/O O R_OUT<0> 2 0 0 3 FB3_17 22 I/O O (unused) 0 0 0 5 FB3_18 (b) Signals Used by Logic in Function Block 1: N64_DATA<0> 4: N64_DATA<4> 7: count_int<0> 2: N64_DATA<1> 5: N64_DATA<5> 8: count_int<1> 3: N64_DATA<3> 6: N64_DATA<6> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs G_OUT<3> ..X...XX................................ 3 G_OUT<4> ...X..XX................................ 3 G_OUT<5> ....X.XX................................ 3 G_OUT<6> .....XXX................................ 3 VSYNC ..X...XX................................ 3 CSYNC X.....XX................................ 3 R_OUT<1> .X....XX................................ 3 R_OUT<0> X.....XX................................ 3 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 7/47 Number of signals used by logic mapping into function block: 7 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB4_1 (b) R_OUT<2> 2 0 0 3 FB4_2 25 I/O O (unused) 0 0 0 5 FB4_3 (b) (unused) 0 0 0 5 FB4_4 (b) R_OUT<3> 2 0 0 3 FB4_5 26 I/O O (unused) 0 0 0 5 FB4_6 (b) (unused) 0 0 0 5 FB4_7 (b) R_OUT<4> 2 0 0 3 FB4_8 27 I/O O (unused) 0 0 0 5 FB4_9 (b) (unused) 0 0 0 5 FB4_10 (b) R_OUT<5> 2 0 0 3 FB4_11 28 I/O O (unused) 0 0 0 5 FB4_12 (b) (unused) 0 0 0 5 FB4_13 (b) R_OUT<6> 2 0 0 3 FB4_14 29 I/O O (unused) 0 0 0 5 FB4_15 33 I/O I (unused) 0 0 0 5 FB4_16 (b) (unused) 0 0 0 5 FB4_17 34 I/O I (unused) 0 0 0 5 FB4_18 (b) Signals Used by Logic in Function Block 1: N64_DATA<2> 4: N64_DATA<5> 6: count_int<0> 2: N64_DATA<3> 5: N64_DATA<6> 7: count_int<1> 3: N64_DATA<4> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs R_OUT<2> X....XX................................. 3 R_OUT<3> .X...XX................................. 3 R_OUT<4> ..X..XX................................. 3 R_OUT<5> ...X.XX................................. 3 R_OUT<6> ....XXX................................. 3 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** FDCPE_B_OUT0: FDCPE port map (B_OUT(0),N64_DATA(0),NOT CLOCK,'0','0',B_OUT_CE(0)); B_OUT_CE(0) <= (NOT count_int(0) AND count_int(1)); FDCPE_B_OUT1: FDCPE port map (B_OUT(1),N64_DATA(1),NOT CLOCK,'0','0',B_OUT_CE(1)); B_OUT_CE(1) <= (NOT count_int(0) AND count_int(1)); FDCPE_B_OUT2: FDCPE port map (B_OUT(2),N64_DATA(2),NOT CLOCK,'0','0',B_OUT_CE(2)); B_OUT_CE(2) <= (NOT count_int(0) AND count_int(1)); FDCPE_B_OUT3: FDCPE port map (B_OUT(3),N64_DATA(3),NOT CLOCK,'0','0',B_OUT_CE(3)); B_OUT_CE(3) <= (NOT count_int(0) AND count_int(1)); FDCPE_B_OUT4: FDCPE port map (B_OUT(4),N64_DATA(4),NOT CLOCK,'0','0',B_OUT_CE(4)); B_OUT_CE(4) <= (NOT count_int(0) AND count_int(1)); FDCPE_B_OUT5: FDCPE port map (B_OUT(5),N64_DATA(5),NOT CLOCK,'0','0',B_OUT_CE(5)); B_OUT_CE(5) <= (NOT count_int(0) AND count_int(1)); FDCPE_B_OUT6: FDCPE port map (B_OUT(6),N64_DATA(6),NOT CLOCK,'0','0',B_OUT_CE(6)); B_OUT_CE(6) <= (NOT count_int(0) AND count_int(1)); FDCPE_CSYNC: FDCPE port map (CSYNC,N64_DATA(0),NOT CLOCK,'0','0',CSYNC_CE); CSYNC_CE <= (NOT count_int(0) AND NOT count_int(1)); FDCPE_G_OUT0: FDCPE port map (G_OUT(0),N64_DATA(0),NOT CLOCK,'0','0',G_OUT_CE(0)); G_OUT_CE(0) <= (count_int(0) AND count_int(1)); FDCPE_G_OUT1: FDCPE port map (G_OUT(1),N64_DATA(1),NOT CLOCK,'0','0',G_OUT_CE(1)); G_OUT_CE(1) <= (count_int(0) AND count_int(1)); FDCPE_G_OUT2: FDCPE port map (G_OUT(2),N64_DATA(2),NOT CLOCK,'0','0',G_OUT_CE(2)); G_OUT_CE(2) <= (count_int(0) AND count_int(1)); FDCPE_G_OUT3: FDCPE port map (G_OUT(3),N64_DATA(3),NOT CLOCK,'0','0',G_OUT_CE(3)); G_OUT_CE(3) <= (count_int(0) AND count_int(1)); FDCPE_G_OUT4: FDCPE port map (G_OUT(4),N64_DATA(4),NOT CLOCK,'0','0',G_OUT_CE(4)); G_OUT_CE(4) <= (count_int(0) AND count_int(1)); FDCPE_G_OUT5: FDCPE port map (G_OUT(5),N64_DATA(5),NOT CLOCK,'0','0',G_OUT_CE(5)); G_OUT_CE(5) <= (count_int(0) AND count_int(1)); FDCPE_G_OUT6: FDCPE port map (G_OUT(6),N64_DATA(6),NOT CLOCK,'0','0',G_OUT_CE(6)); G_OUT_CE(6) <= (count_int(0) AND count_int(1)); FDCPE_HSYNC: FDCPE port map (HSYNC,N64_DATA(1),NOT CLOCK,'0','0',HSYNC_CE); HSYNC_CE <= (NOT count_int(0) AND NOT count_int(1)); PCLOCK <= NOT DSYNC; FDCPE_R_OUT0: FDCPE port map (R_OUT(0),N64_DATA(0),NOT CLOCK,'0','0',R_OUT_CE(0)); R_OUT_CE(0) <= (count_int(0) AND NOT count_int(1)); FDCPE_R_OUT1: FDCPE port map (R_OUT(1),N64_DATA(1),NOT CLOCK,'0','0',R_OUT_CE(1)); R_OUT_CE(1) <= (count_int(0) AND NOT count_int(1)); FDCPE_R_OUT2: FDCPE port map (R_OUT(2),N64_DATA(2),NOT CLOCK,'0','0',R_OUT_CE(2)); R_OUT_CE(2) <= (count_int(0) AND NOT count_int(1)); FDCPE_R_OUT3: FDCPE port map (R_OUT(3),N64_DATA(3),NOT CLOCK,'0','0',R_OUT_CE(3)); R_OUT_CE(3) <= (count_int(0) AND NOT count_int(1)); FDCPE_R_OUT4: FDCPE port map (R_OUT(4),N64_DATA(4),NOT CLOCK,'0','0',R_OUT_CE(4)); R_OUT_CE(4) <= (count_int(0) AND NOT count_int(1)); FDCPE_R_OUT5: FDCPE port map (R_OUT(5),N64_DATA(5),NOT CLOCK,'0','0',R_OUT_CE(5)); R_OUT_CE(5) <= (count_int(0) AND NOT count_int(1)); FDCPE_R_OUT6: FDCPE port map (R_OUT(6),N64_DATA(6),NOT CLOCK,'0','0',R_OUT_CE(6)); R_OUT_CE(6) <= (count_int(0) AND NOT count_int(1)); FDCPE_VSYNC: FDCPE port map (VSYNC,N64_DATA(3),NOT CLOCK,'0','0',VSYNC_CE); VSYNC_CE <= (NOT count_int(0) AND NOT count_int(1)); FDCPE_count_int0: FDCPE port map (count_int(0),count_int_D(0),NOT CLOCK,'0','0'); count_int_D(0) <= (DSYNC AND NOT count_int(0)); FDCPE_count_int1: FDCPE port map (count_int(1),count_int_D(1),NOT CLOCK,'0','0'); count_int_D(1) <= ((DSYNC AND count_int(0) AND NOT count_int(1)) OR (DSYNC AND NOT count_int(0) AND count_int(1))); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC9572XL-5-PC44 -------------------------------- /6 5 4 3 2 1 44 43 42 41 40 \ | 7 39 | | 8 38 | | 9 37 | | 10 36 | | 11 XC9572XL-5-PC44 35 | | 12 34 | | 13 33 | | 14 32 | | 15 31 | | 16 30 | | 17 29 | \ 18 19 20 21 22 23 24 25 26 27 28 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 B_OUT<3> 23 GND 2 B_OUT<4> 24 R_OUT<1> 3 B_OUT<5> 25 R_OUT<2> 4 B_OUT<6> 26 R_OUT<3> 5 HSYNC 27 R_OUT<4> 6 CLOCK 28 R_OUT<5> 7 G_OUT<0> 29 R_OUT<6> 8 G_OUT<1> 30 TDO 9 G_OUT<2> 31 GND 10 GND 32 VCC 11 G_OUT<3> 33 N64_DATA<0> 12 G_OUT<4> 34 N64_DATA<1> 13 G_OUT<5> 35 N64_DATA<2> 14 G_OUT<6> 36 N64_DATA<3> 15 TDI 37 N64_DATA<4> 16 TMS 38 N64_DATA<5> 17 TCK 39 N64_DATA<6> 18 VSYNC 40 PCLOCK 19 DSYNC 41 VCC 20 CSYNC 42 B_OUT<0> 21 VCC 43 B_OUT<1> 22 R_OUT<0> 44 B_OUT<2> Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9572xl-5-PC44 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25