Design Name | main |
Device, Speed (SpeedFile Version) | XC9572XL, -5 (3.0) |
Date Created | Fri Jul 11 01:37:11 2014 |
Created By | Timing Report Generator: version M.70d |
Copyright | Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. |
Notes and Warnings |
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Note: This design contains no timing constraints. |
Note: A default set of constraints using a delay of 0.000ns will be used for analysis. |
Performance Summary | |
---|---|
Min. Clock Period | 5.600 ns. |
Max. Clock Frequency (fSYSTEM) | 178.571 MHz. |
Limited by Clock Pulse Width for CLOCK | |
Clock to Setup (tCYC) | 5.600 ns. |
Pad to Pad Delay (tPD) | 5.000 ns. |
Setup to Clock at the Pad (tSU) | 3.700 ns. |
Clock Pad to Output Pad Delay (tCO) | 3.500 ns. |
Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
---|---|---|---|---|
TS1000 | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_F2F | 0.0 | 5.6 | 30 | 30 |
AUTO_TS_P2P | 0.0 | 5.0 | 11 | 11 |
AUTO_TS_P2F | 0.0 | 4.8 | 13 | 13 |
AUTO_TS_F2P | 0.0 | 2.4 | 10 | 10 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
B_OUT<0>.Q to B_OUT<0>.D | 0.000 | 5.600 | -5.600 |
B_OUT<1>.Q to B_OUT<1>.D | 0.000 | 5.600 | -5.600 |
B_OUT<2>.Q to B_OUT<2>.D | 0.000 | 5.600 | -5.600 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
DSYNC to PCLOCK | 0.000 | 5.000 | -5.000 |
CLOCK to B_OUT<0> | 0.000 | 3.500 | -3.500 |
CLOCK to B_OUT<1> | 0.000 | 3.500 | -3.500 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
DSYNC to count_int<0>.D | 0.000 | 4.800 | -4.800 |
DSYNC to count_int<1>.D | 0.000 | 4.800 | -4.800 |
N64_DATA<0> to B_OUT<0>.D | 0.000 | 4.800 | -4.800 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
B_OUT<0>.Q to B_OUT<0> | 0.000 | 2.400 | -2.400 |
B_OUT<1>.Q to B_OUT<1> | 0.000 | 2.400 | -2.400 |
B_OUT<2>.Q to B_OUT<2> | 0.000 | 2.400 | -2.400 |
Clock | fEXT (MHz) | Reason |
---|---|---|
CLOCK | 178.571 | Limited by Clock Pulse Width for CLOCK |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
DSYNC | 3.700 | 0.000 |
N64_DATA<0> | 3.700 | 0.000 |
N64_DATA<1> | 3.700 | 0.000 |
N64_DATA<2> | 3.700 | 0.000 |
N64_DATA<3> | 3.700 | 0.000 |
N64_DATA<4> | 3.700 | 0.000 |
N64_DATA<5> | 3.700 | 0.000 |
N64_DATA<6> | 3.700 | 0.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
B_OUT<0> | 3.500 |
B_OUT<1> | 3.500 |
B_OUT<2> | 3.500 |
B_OUT<3> | 3.500 |
B_OUT<4> | 3.500 |
B_OUT<5> | 3.500 |
B_OUT<6> | 3.500 |
CSYNC | 3.500 |
HSYNC | 3.500 |
VSYNC | 3.500 |
Source | Destination | Delay |
---|---|---|
B_OUT<0>.Q | B_OUT<0>.D | 5.600 |
B_OUT<1>.Q | B_OUT<1>.D | 5.600 |
B_OUT<2>.Q | B_OUT<2>.D | 5.600 |
B_OUT<3>.Q | B_OUT<3>.D | 5.600 |
B_OUT<4>.Q | B_OUT<4>.D | 5.600 |
B_OUT<5>.Q | B_OUT<5>.D | 5.600 |
B_OUT<6>.Q | B_OUT<6>.D | 5.600 |
count_int<0>.Q | B_OUT<0>.D | 5.600 |
count_int<0>.Q | B_OUT<1>.D | 5.600 |
count_int<0>.Q | B_OUT<2>.D | 5.600 |
count_int<0>.Q | B_OUT<3>.D | 5.600 |
count_int<0>.Q | B_OUT<4>.D | 5.600 |
count_int<0>.Q | B_OUT<5>.D | 5.600 |
count_int<0>.Q | B_OUT<6>.D | 5.600 |
count_int<0>.Q | CSYNC.CE | 5.600 |
count_int<0>.Q | HSYNC.CE | 5.600 |
count_int<0>.Q | VSYNC.CE | 5.600 |
count_int<0>.Q | count_int<0>.D | 5.600 |
count_int<0>.Q | count_int<1>.D | 5.600 |
count_int<1>.Q | B_OUT<0>.D | 5.600 |
count_int<1>.Q | B_OUT<1>.D | 5.600 |
count_int<1>.Q | B_OUT<2>.D | 5.600 |
count_int<1>.Q | B_OUT<3>.D | 5.600 |
count_int<1>.Q | B_OUT<4>.D | 5.600 |
count_int<1>.Q | B_OUT<5>.D | 5.600 |
count_int<1>.Q | B_OUT<6>.D | 5.600 |
count_int<1>.Q | CSYNC.CE | 5.600 |
count_int<1>.Q | HSYNC.CE | 5.600 |
count_int<1>.Q | VSYNC.CE | 5.600 |
count_int<1>.Q | count_int<1>.D | 5.600 |
Source Pad | Destination Pad | Delay |
---|---|---|
DSYNC | PCLOCK | 5.000 |