********** Mapped Logic ********** |
FDCPE_B_OUT0: FDCPE port map (B_OUT(0),N64_DATA(0),NOT CLOCK,'0','0',B_OUT_CE(0));
B_OUT_CE(0) <= (NOT count_int(0) AND count_int(1)); |
FDCPE_B_OUT1: FDCPE port map (B_OUT(1),N64_DATA(1),NOT CLOCK,'0','0',B_OUT_CE(1));
B_OUT_CE(1) <= (NOT count_int(0) AND count_int(1)); |
FDCPE_B_OUT2: FDCPE port map (B_OUT(2),N64_DATA(2),NOT CLOCK,'0','0',B_OUT_CE(2));
B_OUT_CE(2) <= (NOT count_int(0) AND count_int(1)); |
FDCPE_B_OUT3: FDCPE port map (B_OUT(3),N64_DATA(3),NOT CLOCK,'0','0',B_OUT_CE(3));
B_OUT_CE(3) <= (NOT count_int(0) AND count_int(1)); |
FDCPE_B_OUT4: FDCPE port map (B_OUT(4),N64_DATA(4),NOT CLOCK,'0','0',B_OUT_CE(4));
B_OUT_CE(4) <= (NOT count_int(0) AND count_int(1)); |
FDCPE_B_OUT5: FDCPE port map (B_OUT(5),N64_DATA(5),NOT CLOCK,'0','0',B_OUT_CE(5));
B_OUT_CE(5) <= (NOT count_int(0) AND count_int(1)); |
FDCPE_B_OUT6: FDCPE port map (B_OUT(6),N64_DATA(6),NOT CLOCK,'0','0',B_OUT_CE(6));
B_OUT_CE(6) <= (NOT count_int(0) AND count_int(1)); |
FDCPE_CSYNC: FDCPE port map (CSYNC,N64_DATA(0),NOT CLOCK,'0','0',CSYNC_CE);
CSYNC_CE <= (NOT count_int(0) AND NOT count_int(1)); |
FDCPE_G_OUT0: FDCPE port map (G_OUT(0),N64_DATA(0),NOT CLOCK,'0','0',G_OUT_CE(0));
G_OUT_CE(0) <= (count_int(0) AND count_int(1)); |
FDCPE_G_OUT1: FDCPE port map (G_OUT(1),N64_DATA(1),NOT CLOCK,'0','0',G_OUT_CE(1));
G_OUT_CE(1) <= (count_int(0) AND count_int(1)); |
FDCPE_G_OUT2: FDCPE port map (G_OUT(2),N64_DATA(2),NOT CLOCK,'0','0',G_OUT_CE(2));
G_OUT_CE(2) <= (count_int(0) AND count_int(1)); |
FDCPE_G_OUT3: FDCPE port map (G_OUT(3),N64_DATA(3),NOT CLOCK,'0','0',G_OUT_CE(3));
G_OUT_CE(3) <= (count_int(0) AND count_int(1)); |
FDCPE_G_OUT4: FDCPE port map (G_OUT(4),N64_DATA(4),NOT CLOCK,'0','0',G_OUT_CE(4));
G_OUT_CE(4) <= (count_int(0) AND count_int(1)); |
FDCPE_G_OUT5: FDCPE port map (G_OUT(5),N64_DATA(5),NOT CLOCK,'0','0',G_OUT_CE(5));
G_OUT_CE(5) <= (count_int(0) AND count_int(1)); |
FDCPE_G_OUT6: FDCPE port map (G_OUT(6),N64_DATA(6),NOT CLOCK,'0','0',G_OUT_CE(6));
G_OUT_CE(6) <= (count_int(0) AND count_int(1)); |
FDCPE_HSYNC: FDCPE port map (HSYNC,N64_DATA(1),NOT CLOCK,'0','0',HSYNC_CE);
HSYNC_CE <= (NOT count_int(0) AND NOT count_int(1)); |
PCLOCK <= NOT DSYNC; |
FDCPE_R_OUT0: FDCPE port map (R_OUT(0),N64_DATA(0),NOT CLOCK,'0','0',R_OUT_CE(0));
R_OUT_CE(0) <= (count_int(0) AND NOT count_int(1)); |
FDCPE_R_OUT1: FDCPE port map (R_OUT(1),N64_DATA(1),NOT CLOCK,'0','0',R_OUT_CE(1));
R_OUT_CE(1) <= (count_int(0) AND NOT count_int(1)); |
FDCPE_R_OUT2: FDCPE port map (R_OUT(2),N64_DATA(2),NOT CLOCK,'0','0',R_OUT_CE(2));
R_OUT_CE(2) <= (count_int(0) AND NOT count_int(1)); |
FDCPE_R_OUT3: FDCPE port map (R_OUT(3),N64_DATA(3),NOT CLOCK,'0','0',R_OUT_CE(3));
R_OUT_CE(3) <= (count_int(0) AND NOT count_int(1)); |
FDCPE_R_OUT4: FDCPE port map (R_OUT(4),N64_DATA(4),NOT CLOCK,'0','0',R_OUT_CE(4));
R_OUT_CE(4) <= (count_int(0) AND NOT count_int(1)); |
FDCPE_R_OUT5: FDCPE port map (R_OUT(5),N64_DATA(5),NOT CLOCK,'0','0',R_OUT_CE(5));
R_OUT_CE(5) <= (count_int(0) AND NOT count_int(1)); |
FDCPE_R_OUT6: FDCPE port map (R_OUT(6),N64_DATA(6),NOT CLOCK,'0','0',R_OUT_CE(6));
R_OUT_CE(6) <= (count_int(0) AND NOT count_int(1)); |
FDCPE_VSYNC: FDCPE port map (VSYNC,N64_DATA(3),NOT CLOCK,'0','0',VSYNC_CE);
VSYNC_CE <= (NOT count_int(0) AND NOT count_int(1)); |
FDCPE_count_int0: FDCPE port map (count_int(0),count_int_D(0),NOT CLOCK,'0','0');
count_int_D(0) <= (DSYNC AND NOT count_int(0)); |
FDCPE_count_int1: FDCPE port map (count_int(1),count_int_D(1),NOT CLOCK,'0','0');
count_int_D(1) <= ((DSYNC AND count_int(0) AND NOT count_int(1)) OR (DSYNC AND NOT count_int(0) AND count_int(1))); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |