Environment Settings | ||
Environment Variable | xst | ngdbuild |
PATHEXT | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC |
.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC |
Path | C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64; C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64; C:\Xilinx\12.3\ISE_DS\PlanAhead\bin; C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64; C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64; C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64; C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64; C:\Xilinx\12.3\ISE_DS\common\bin\nt64; C:\Xilinx\12.3\ISE_DS\common\lib\nt64; C:\ispLEVER_Classic1_7\ispcpld\bin; C:\ispLEVER_Classic1_7\ispFPGA\bin\nt; C:\ispLEVER_Classic1_7\active-hdl\BIN; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files (x86)\Java\jdk1.6.0_45\bin; C:\Program Files (x86)\ATI Technologies\ATI.ACE\Core-Static |
C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64; C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64; C:\Xilinx\12.3\ISE_DS\PlanAhead\bin; C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64; C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64; C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64; C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64; C:\Xilinx\12.3\ISE_DS\common\bin\nt64; C:\Xilinx\12.3\ISE_DS\common\lib\nt64; C:\ispLEVER_Classic1_7\ispcpld\bin; C:\ispLEVER_Classic1_7\ispFPGA\bin\nt; C:\ispLEVER_Classic1_7\active-hdl\BIN; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files (x86)\Java\jdk1.6.0_45\bin; C:\Program Files (x86)\ATI Technologies\ATI.ACE\Core-Static |
XILINX | C:\Xilinx\12.3\ISE_DS\ISE\ | C:\Xilinx\12.3\ISE_DS\ISE\ |
XILINX_DSP | C:\Xilinx\12.3\ISE_DS\ISE | C:\Xilinx\12.3\ISE_DS\ISE |
XILINX_EDK | C:\Xilinx\12.3\ISE_DS\EDK | C:\Xilinx\12.3\ISE_DS\EDK |
XILINX_PLANAHEAD | C:\Xilinx\12.3\ISE_DS\PlanAhead | C:\Xilinx\12.3\ISE_DS\PlanAhead |
Synthesis Property Settings | |||
Switch Name | Property Name | Value | Default Value |
-ifn | main.prj | ||
-ifmt | mixed | MIXED | |
-ofn | main | ||
-ofmt | NGC | NGC | |
-p | xc9500xl | ||
-top | main | ||
-opt_mode | Optimization Goal | Speed | Speed |
-opt_level | Optimization Effort | 1 | 1 |
-iuc | Use synthesis Constraints File | NO | NO |
-keep_hierarchy | Keep Hierarchy | Yes | YES |
-netlist_hierarchy | Netlist Hierarchy | As_Optimized | As_Optimized |
-rtlview | Generate RTL Schematic | Yes | NO |
-bus_delimiter | Bus Delimiter | <> | <> |
-verilog2001 | Verilog 2001 | YES | YES |
-fsm_extract | YES | YES | |
-fsm_encoding | Auto | AUTO | |
-safe_implementation | No | NO | |
-resource_sharing | YES | YES | |
-iobuf | YES | YES | |
-equivalent_register_removal | YES | YES |
Translation Property Settings | |||
Switch Name | Property Name | Value | Default Value |
-intstyle | ise | None | |
-dd | _ngo | None | |
-p | xc9572xl-PC44-5 | None | |
-uc | main.ucf | None |
Operating System Information | ||
Operating System Information | xst | ngdbuild |
CPU Architecture/Speed | Intel(R) Core(TM) i5-3330 CPU @ 3.00GHz/3000 MHz | Intel(R) Core(TM) i5-3330 CPU @ 3.00GHz/3000 MHz |
Host | oerg866-PC | oerg866-PC |
OS Name | Microsoft | Microsoft |
OS Release | major release (build 7600) | major release (build 7600) |